Computer systems which utilize programmable interrupt controllers (PICs) in a single processor environment are well known in the prior art. Intel Corporations part number 8259A is an example of a PIC used in such single processor systems. The PICs serve as interface units between the input/output (I/O) devices and the processor in handling interrupt requests. The PIC accepts an interrupt request from the I/O devices and issues an interrupt request to the processor on an interrupt line. On receiving the interrupt request from the PIC, the processor generally initiates an interrupt acknowledge cycle. In the interrupt acknowledge cycle, the PIC sends an interrupt vector to the processor, which identifies an interrupt handler routine in the processor. The processor executes the interrupt handler routine to handle the interrupt pending on the I/O device.
With the advent of multi-processor computer systems, interrupt management systems that dynamically distribute the interrupt among the processors have been implemented. Intel's Advanced Programmable Interrupt Controller Architecture is an example of such a system. Typically, such an interrupt management system includes at least three functional components: 1. Advanced Programmable Interrupt Controllers (APIC) that provide interface lines on which I/O devices or PICs send interrupts into the system 2. Processors with modules to receive and service the interrupt requests from the I/O devices and 3, a bus that connects the processors and the APICs.
When an interrupt is pending, the I/O device or the PIC that is connected directly to the APIC sends an interrupt signal to the APIC. In response, the APIC broadcasts an interrupt request data packet on the bus. The interrupt request data packet contains a first field set to the identification number of the destination processor, a second field set to identify the type of device causing the interrupt and a third field set to the interrupt vector.
On receiving the interrupt request data packet, each of the processors examines the first field to determine if the interrupt request is directed to it. The processor then uses the interrupt vector in the third field to determine the address of the interrupt service routine. The processor executes the interrupt service routine to process the interrupt.
One of the basic requirements of a multi-processor system is to support PICs so as to be backward compatible with the prior application base. In this case, the PICs generally interlace with the APICs using the interface lines of the APIC. The PIC is connected to the I/O devices and provides the interface between the APIC and these I/O devices. The APIC may have other I/O devices connected directly on the other interface lines.
When an I/O device connected to a PIC has an interrupt pending to be processed, it sends an interrupt request signal to the PIC. In response, the PIC sends another signal to the APIC on the interface lines. The APIC broadcasts an interrupt request data packet on the bus to which all the processors couple. In the interrupt request data packet, the first field is set to the identification number of processor to which the interrupt is to be directed to; and the second field is set to identify the type of device causing the interrupt. The APIC does not use the third field that is used to specify an interrupt vector. The processor, which processes the interrupt, gets the interrupt vector from the PIC in a subsequent interrupt acknowledge cycle. The processor determines an interrupt service routine based on the interrupt vector and processes the interrupt pending on the I/O device by executing the service routine.
However, these multi-processor based systems suffer from the drawback that only one PIC can be supported in a given multi-processor system. This is because there is no field in the interrupt request data packet to identify the PIC that initially caused the APIC to send the interrupt request data packet. What is needed is a mechanism to identify the PIC that has sent the interrupt request when multiple PICs are present in the multi-processor system so that the resulting interrupt acknowledge cycle can be directed to the identified PIC. This will enable the multi-processor system to support multiple PICs.